a$)$ Suppose we have a processor with a base of CPI of $20$ and $0$ clock rate of $5$ghz$,$ assuming all reference hit in the primary cache. Assume a main memory access time of $100$ns$,$ including all the miss handling. suppose the miss rate per instruction at the primary cache is $4\%.$ how much faster will the processor be if we add secondary cache that has $6$ns access time for either a hit or a miss and is large enough to reduce the miss rate to main memory to $1\%?$ b$)$ consider an unpipelined processor, assume that it has $1$ns clock cycle and that it uses $5$ cycles for ALU operations and $5$ cycles for branches and $6$ cycles for memory operations. Assume that relative frequencies of these operation are $40\%,40\%$ and $20\%$ respectively, suppose that due to clock shew and set up pipelining, the processor adds $0\mathrm{.}25$ns of overhead of the clock. ignoring any latency impact how much speedup In the instruction execution rate da I$$ll we gain from pipeline