a$.$ Suppose we have a processor with a base CPI of $2\mathrm{.}0,$ and a clock rate of $5$ GHz

assuming all references hit in the primary cache. Assume a main memory access time

of $100$ ns $,$ including all the miss handling. Suppose the miss rate per instruction at th

primary cache is $4\%.$ How much faster will the processor be if we add a secondary

cache that has a $6$ ns access time for either a hit or a miss and is large enough to

reduce the miss rate to main memory to $1\%?$

$[5$ Marks$]$

b$.$ Consider an unpipelined processor. Assume that it has $1-$ns clock cycle and that it

uses $5$ cycles for ALU operations and $5$ cycles for branches and $6$ cycles for memory

operations. Assume that the relative frequencies of these operations are $40\%,40\%$

and $20\%$ respectively. Suppose that due to clock skew and set up$,$ pipelining the

processor adds $0\mathrm{.}25$ ns of overhead to the clock. lgnoring any latency impact, how

much speed up in the instruction execution rate will we gain from a pipeline?

Marks$]$