a Suppose we have a processor with a base $\frac{C}{P}$I of $2\mathrm{.}0,$ and a clock rate of $5$ GHz

assuning all. references nt in the primary cache Assume a main memory access time

of $100$ ns $,$ including ail the miss hand ing. Suppose the miss rate per instruction at the

primary cache is $4\%.$ How much faste' will the processor be if we add a secondary

kache that has a $6$ ns access time for either a hit or a miss and is large enough to

reduce the miss rate to mar memoy to $1\%?$

$[5$ Marks$]$

b$.$ Consider an unpipeined processo: Assume that it has $1-$ns clock cycle and that it

uses $5$ cycles for ALU operations and $5$ cydles for branches and $6$ cycles for memory

operations. Assure that the elative frequencies of these operations are $40\%,40\%$

and $20\%$ respectively. Suppose that due to clook skew and set up$,$ pipelining the

processor adds $0\mathrm{.}25$ ns of overhead to the cock. Ignonng any latency impact, how

much speed uo in the instruction execution rate wil we gain from a pipeline?

Marks$]$