Question: A virtual address is 40 bits wide. The virtual memory manager uses a multi-level page table. Page size is 4KB. The PTE is 4 bytes.

A virtual address is 40 bits wide. The virtual memory manager

A virtual address is 40 bits wide. The virtual memory manager uses a multi-level page table. Page size is 4KB. The PTE is 4 bytes. The PDE is 4 bytes. Each piece of the multi-level page table must fit in a page. Assume a valid bit, a present bit, a dirty bit, and three protection bits. (a) Compute the width of the offset size in bits. Explain your computation. (b) Compute the width of the VPN field in bits. Explain your computation. (c) Compute the number of PTEs that can be put in a single page. Explain your computation. (d) Compute the width of the page table index in bits. Explain your computation. (e) Compute the number of levels of this multi-level page table. Explain your computation. (f) Compute the width of the topmost page directory index in bits. Explain your computation. (g) Compute the width of the next-level page directory index in bits. Explain your computation

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