(a) Why must Processor designers release ISA Specifications? Briefly Explain. (b) Below is the MIPs assembly of a function (C-code). funct: addiu $sp,$sp, -8 sw $fp, 4($sp) move $fp,$sp sw $4,8 ($fp) lw $t2,8($fp) nop slt St2, $t2,4 bne $t2, $0, $L2 nop li $t2,1 j SL3 nop $L2: li $t2,2 $L3: move $sp,$fp lw $fp, 4($sp) addiu $sp,$sp, 8 j Sra Figure 1. MIPS Assembly Code of 'Function (i) Describe each of the 5 assembly code blocks (denoted by a line space) in Figure 1 and give the C-code function. (ii) If the C-code was extended to be used with an array, what MIPS instructions would be used to load the address 0x80042001 into t2. The ALU is a critical element in the processor. Explain using a diagram of a 1-bit ALU how branching instructions are supported. (d) Draw a table to show how an 8 one-word direct mapped cache is filled from empty for the following series of memory addresses using the Least Recently Used policy. Calculate the hit rate after all cache operations. 4,7,8, 2, 12, 13, 2, 4, 7,3 (e) Draw the table from Part (d) to show how 2-way set associative is filled and calculate the hit rate. The new Apple MI processor utilises 4 x 128 NEOS processors with a CPI of 0.25 due to the multicore system but memory operations utilise 30% of instructions taking I cycle. Find the effective CPI and comment on future design needs