Exercise 4.2 The basic single-cycle MIPS implementation in Figure 4.2 can only implement some instructions. New instructions can be added to an existing ISA, but the decision whether or not to do that depends, among other things, on the cost and complexity such an addition introduces into the processor datapath and control.

The fi rst three problems in this exercise refer to this new instruction:

Instruction Interpretation

a. add3 Rd,Rs,Rt,Rx Reg[Rd]=Reg[Rs]+Reg[Rt]+Reg[Rx]

b. sll Rt,Rd,Shift Reg[Rd]= Reg[Rt] << Shift (shift left by Shift bits)

4.2.1 [10] <4.1> Which existing blocks (if any) can be used for this instruction?

4.2.2 [10] <4.1> Which new functional blocks (if any) do we need for this instruction?

4.2.3 [10] <4.1> What new signals do we need (if any) from the control unit to support this instruction?

When processor designers consider a possible improvement to the processor datapath, the decision usually depends on the cost/performance tradeoff. In the following three problems, assume that we are starting with a datapath from Figure 4.2, where I-Mem, Add, Mux, ALU, Regs, D-Mem, and Control blocks have latencies of 400ps, 100ps, 30ps, 120ps, 200ps, 350ps, and 100ps, respectively, and costs of 1000, 30, 10, 100, 200, 2000, and 500, respectively. The remaining three problems in this exercise refer to the following processor improvement:

Improvement Latency Cost Benefi t

a. Faster Add –20ps for Add units +20 per Add unit Replaces existing Add units with faster ones.

b. Larger Registers +100ps for Regs +200 for Regs Fewer loads and stores needed to save and restore register values. This results in 5% fewer instructions.
4.2.4 [10] <4.1> What is the clock cycle time with and without this improvement?
4.2.5 [10] <4.1> What is the speed-up achieved by adding this improvement?
4.2.6 [10] <4.1> Compare the cost/performance ratio with and without this improvement.