A workstation uses a 15 MHz processor with a claimed 10 MIPS rating to execute a given program mix. Assume one cycle delay for each memory access.

a. What is the effective CPI of this computer?

b. Suppose the processor is upgraded with a 30 MHz clock. However, the speed of the memory subsystem remains unchanged, and consequently two clock cycles are needed per memory access. If 30% of the instructions require one memory access and another 5% require two memory accesses per instruction, what is the performance (new MIPS rating) of the upgraded processor with a compatible instruction set and equal instruction counts in the given program mix?