Problem 1.3 A workstation uses a 1.5 GHz pro- cessor with a claimed 1000-MIPS rating to execute a given program mix. Assume a one-cycle delay for each memory access. (a) What is the effective CPI of this computer? (b) Suppose the processor is being upgraded with a 3.0 GHz clock. However, even with faster cache, two dock cycles are needed per memory access. If 30% of the instructions require one memory access and another 5% require two memory accesses per instruction, what is the performance of the upgraded processor with a compatible instruction set and equal instruction counts in the given program mix