(a) Write the assembly code to implement an atomic compare&swap using load-linked and store-conditional. Compare&swap (r1,r2,x) works as follows: Typically r1 is O (for unlocked) and r2 is 1 (for locked) 1. If (r1 = MEMIx)) then { r2 = MEM[x] MEM[x] = r2 FYI: atomic swap is implemented in some systems (e.g., IBM POWER and Intel x86). (b) Test-and-set incurs high traffic while spin waiting. What happens to compare&swap? (a) Write the assembly code to implement an atomic compare&swap using load-linked and store-conditional. Compare&swap (r1,r2,x) works as follows: Typically r1 is O (for unlocked) and r2 is 1 (for locked) 1. If (r1 = MEMIx)) then { r2 = MEM[x] MEM[x] = r2 FYI: atomic swap is implemented in some systems (e.g., IBM POWER and Intel x86). (b) Test-and-set incurs high traffic while spin waiting. What happens to compare&swap