a)(6 pts) Draw the logic diagram that represents minimum two-level logic needed to implement the following Verilog dataflow description. b) (1 pt) what type of circuit is this? (i.e. what does it do?) 4. /7 Combinational Circuit 2: Dataflow Verilog Description module comb_ckt 2 (y, a, b, c, d, e, f); input a, b, c, d, e, f; output y; wire nl, n2, n3, n4, n5; 11 5 11 6 assign n1 (~e & ~f) & a; assign n2 = e ~f; assign n3 -e &f& assign n4 = ~d ~e ~f; assign n5 - ~n2 & b; assign y= n1 I n3 ~n4 n5 ; endmodule