Adder Delay and Frequency. Assuming the adder delays from Exercise $1,$ what is the fastest frequency at which you could reliably calculate a $64-$bit addition for each of the adders in Exercise $1?$ If the circuit cannot run reliably at any frequency, state that.

Use the following flip$-$flop characteristics: $t_{pcq}=100ps,t_{ccq}=50ps,t_{\text{s}\text{e}\text{t}\text{u}\text{p}}=70ps,t_{\text{h}\text{o}\text{l}\text{d}}=60$ ps$.$ The adder circuit looks as shown in Figure $1.$ At each clock edge, the adder receives new inputs $($operands $A,B,$ and $C_{in}),$ and at the following clock edge, the adder produces the result $($ S and Cout $)$ of that calculation. Be sure to complete the entire timing analysis $($analyzing both hold time and setup time constraints$)$ for each circuit.