All FPGAs include flip$-$flops that are available for implementing a user's circuit. We will show how to make

use of these flip$-$flops in Part IV of this assignment. But first we will show how storage elements can be

created in an FPGA without using its dedicated flip$-$flops. Fig. $5$ depicts a gated D latch circuit. Two styles

of Verilog code that can be used to describe this circuit are given in Fig. $6.$ Part a of the figure specifies the

latch by instantiating logic gates, and part b uses logic expressions to create the same circuit. If this latch

is implemented in an FPGA that has $4-$input lookup tables $($LUTs$),$ then only one lookup table is needed.

Fig. $6$a$.$ Instantiating logic gates for the D latch.

Fig. $6$ b$.$ Specifying the D latch by using logic expressions

Although the latch can be correctly realized in one $4-$input LUT, this implementation does not allow its

internal signals, such as $R$ g and $S$ g$,$ to be observed, because they are not provided as outputs from the

LUT. To preserve these internal signals in the implemented circuit, it is necessary to include a compile

directive in the code. In Fig. $6$ the directive $//$ is included to instruct the Quartus II

compiler to use separate logic elements for each of the signals R$\_$g$,$ S$\_$g$,$Qa$,$ and Qb$.$ Compiling the code

produces the circuit with four $4-$LUTs, one for each assign statement.

Fig. $7$ shows a circuit with three different storage elements: a gated D latch, a positive$-$edge triggered D

flip$-$flop, and a negative$-$edge triggered D flip$-$flop. Implement and simulate the circuit in Fig. $7$ by using the Quartus Il software as follows:$1.$ The project for this part is provided in the starter kit. Open the project named port$3$ in the port$3$ subdirectory to begin your work$\mathrm{.}2.$ Write a Verilog file that instantiates the three storage elements. For this part you should no longer include the $/$ synthesis keep $*/$ directive in your Verilog code, because you will not be describing the exact structure of flip$-$flops. Instead, you should use a style of Verilog code that will allow the Verilog compiler $($in the Quartus II software$)$ to automatically instantiate flip$-$flops that are provided as part of the FPGA logic elements. Such Verilog code is often called behavioral code, because it specifies a desired circuit behavior rather than an exact circuit structure. As an example, Fig. $8$ gives a behavioral style of Verilog code that specifies the gated D latch in Fig. $6.$ This latch can be implemented in one $4-$input lookup table. Use a similar style of code to specify the flip$-$flops in Fig. $7\mathrm{.}3.$ Compile your project$\mathrm{.}4.$ You may wish to use the Quartus Technology Map Viewer to examine the compiled circuit, by using the command Tools $>$ Netlist Viewer $>$ Technology Map Viewer$\mathrm{.}5.$ Create a Vector Waveform File $(.$vwf$)$ which specifies the inputs and outputs of the circuit. You need to show it in the report. Draw the inputs D and Clock as indicated in Fig. $7.$ Use functional simulation to obtain the three output signals. Observe the different behavior of the three storage elements. $($Also you can simulate your circuit in Modelsim software$)$module D latch $($D$,$ Clk$,$ Q$)$;input D$,$ Clk;output reg Q:always @ $($D$,$ Clk$)$if $($Clk$)$Q$=$D;endmoduleFig. $8.$ A behavioral style of Verilog code that specifies a gated D latch