An ARM CortexA$77$ processor has a $13-$stage pipeline and a clock frequency of $2\mathrm{.}6$ GHz$.$

An ARM Neoverse E$1$ processor version has a $10-$stage pipeline and a clock frequency of $3\mathrm{.}1$ GHz$.$

Both processors use a four$-$issue pipeline.

For a given sequence of instructions, the CortexA$77$ has an IPC $($Instructions Per Cycle$)$ rate of $3.$ For the same sequence of instructions, the Neoverse E$1$ has an IPC of $2.$ Assume that both processors sustain the same IPC rate throughout the execution of the program, i$.$e$.$ they issue $3($CortexA$77),$ and $2($Neoverse E$1)$ instructions per cycle throughout execution. What is the latency of a single instruction on the CortexA$77$ in nanoseconds? What is the latency of a single instruction on the NeoVerse E$1$ in nanoseconds? Round to two digits. Assume the two processors execute a sequence of instructions starting with an empty pipeline. What is the minimum number of instructions the two processors need to execute so that the performance of the CortexA$77$ is higher than that of the Neoverse E$1?$