An IEEE Manchester encoder produces a low-to-high transition when the input is '1' or a high-to-low...

  

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An IEEE Manchester encoder produces a low-to-high transition when the input is '1' or a high-to-low transition when it is '0', as illustrated in i gure 5.19 for the sequence "01001". Note that each input value lasts two clock periods. Observe also the presence of a dv bit, which dei nes the extent of the vector to be encoded (dashed lines in y indicate "don't care" values). To be more realistic, dv is produced at the same time that the i rst valid bit is presented; additionally, a small propagation delay is included between clock transitions and corresponding responses. Assume that the machine too must operate at the positive clock edge. a) Draw a state transition diagram for a Moore machine capable of implementing this encoder. b) Redraw the illustrative timing diagram of i gure 5.19 for your Moore machine, including in it a plot for pr_state. Does the Moore circuit behave exactly as in i gure 5.19, or is y one clock cycle delayed? c) Redo the design, this time employing a Mealy machine. dv Figure 5.19 ¹1 '0' An IEEE Manchester encoder produces a low-to-high transition when the input is '1' or a high-to-low transition when it is '0', as illustrated in i gure 5.19 for the sequence "01001". Note that each input value lasts two clock periods. Observe also the presence of a dv bit, which dei nes the extent of the vector to be encoded (dashed lines in y indicate "don't care" values). To be more realistic, dv is produced at the same time that the i rst valid bit is presented; additionally, a small propagation delay is included between clock transitions and corresponding responses. Assume that the machine too must operate at the positive clock edge. a) Draw a state transition diagram for a Moore machine capable of implementing this encoder. b) Redraw the illustrative timing diagram of i gure 5.19 for your Moore machine, including in it a plot for pr_state. Does the Moore circuit behave exactly as in i gure 5.19, or is y one clock cycle delayed? c) Redo the design, this time employing a Mealy machine. dv Figure 5.19 ¹1 '0'

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State Transition Diagram for Moore Machine Illustrative Timing Diagram wit... View the full answer