Question: An L2 cache is connected to a memory system via a 256-bit wide bus. The memory delay is 60 CPU cycles. How many cycles are

An L2 cache is connected to a memory system via a

An L2 cache is connected to a memory system via a 256-bit wide bus. The memory delay is 60 CPU cycles. How many cycles are required to transfer a 32-byte block from the memory to the L2 cache if sending the address requires 1 CPU cycle and each bus transfer requires 4 CPU cycles? Answer: 213

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