Consider a processor that run at 3 GHz and has a base CPI (i.e., CPI execution) of 1.2 (with perfect caches). The only instructions that access memory are loads (20% of all instructions) and stores (5% of all instructions). The memory system for this computer has the following characteristics:

L1 cache

32 KB I-cache, direct-mapped, 64-byte blocks, 4% miss-rate, and requires 3-cycle hit time (no penalty on hits)

32 KB D-cache, direct-mapped, write-back, 64-byte blocks, 6% miss rate, and requires 3-cycle hit time (no penalty on hits). Assume a write buffer between D-cache and L2 cache that eliminates additional stalls require to write back dirty blocks from L1 cache to L2 cache.

L2 cache

512 KB unified L2 cache, write-back, 64-byte blocks, and access time of 12 clock cycles. L2 cache is connected to L1 cache by a 256-bit data bus that runs at 1.6 GHz and can transfer one 256-bit word per bus cycle.

Of all memory references sent to L2 cache, 51% are satisfied without going to main memory. Also, 50% of all blocks replaced are dirty.

Main Memory

64-bit wide main memory has an access latency of 40 ns, after which any number of bus words may be transferred at the rate of one per cycle on the 64-bit wide 533 MHz main memory bus.

(a) What is the average memory access time for instruction accesses? - If miss penalty is (1/0.96)*12, why???

(b) What is the average memory access time for data accesses?

(c) What is the overall CPI, including memory accesses?

(d) Suppose you are considering replacing the 3 GHz CPU with one that runs at 4 GHz, but is otherwise identical. How much faster does the system run with a faster processor? Assume the L1 cache still has no hit penalty, and that the speed of the L2 cache, main memory, and bus remains the same