An unpipelined processor can be pipelined by breaking it down into five parallel stages: instruction fetch $($IF$),$ instruction decode $($ID$),$ execute $($EX$),$ memory access $($MEM$),$ and writeback $($WB$).$ These stages will require, respectively, $170$ ps$,220$ ps$,200$ ps$,205$ ps$,$ and $195$ ps$.$

Fill in the blanks below. Do not include units in your answer; units are already given for you.

What is the clock cycle time of the unpipelined processor?

ps

What is the clock frequency of the unpipelined processor $($please round to two decimal places$)?$

GHz

What is the clock cycle time of the pipelined processor?

ps

What is the clock frequency of the pipelined processor $($please round to two decimal places$)$

GHz