Question: Design a micro controller instruction cycle pipeline to execute an embedded program which has 3 0 0 instructions. Each instruction has a uniform period and

Design a micro controller instruction cycle pipeline to execute an embedded program which has 300 instructions. Each instruction has a uniform period and has 5 pipeline stages in the following order Instruction Fetch (IF), Instruction Decode (ID), Execute (Ex), Memory Access (MEM) and Register Write Back (WB). The fetch operation takes 2 clock cycles, decode operation takes 2 clock cycles, execution operation takes 8 cycles, memory access takes 2 cycles and register write back takes 2 cycles. (a) With necessary diagrams, calculate the total number of clock cycles that will take to execute the program with pipeline. (b) If the micro controller is given a clock with input clock frequency 2.5 GHz, what is the maximum clock frequency with which the micro controller can operate? (c) If the instruction pipeline is flushed after every 30 instructions, calculate the total number of clock cycles taken. (d) Suggest on improvement of performance of the system

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