AND SIMULATION WAVEFORM

Q) For the following problem please write the Verilog program and its testbench # program only With a resource allocation constrained to one multiplier/divider, one subtractor, and one shift to perform the multiplication by 2, derive the Verilog design of the FDA that computes the equation: c= 2x/3 - y/3x2 Furthermore, perform the performance analysis if the equation is to be iterated for 50 times. Given the propagation delays for the components are multiplier/divider is 50 ns, subtractor is 10 ns, shifter is 5 ns, and the register setup time is 5 ns. Q) For the following problem please write the Verilog program and its testbench # program only With a resource allocation constrained to one multiplier/divider, one subtractor, and one shift to perform the multiplication by 2, derive the Verilog design of the FDA that computes the equation: c= 2x/3 - y/3x2 Furthermore, perform the performance analysis if the equation is to be iterated for 50 times. Given the propagation delays for the components are multiplier/divider is 50 ns, subtractor is 10 ns, shifter is 5 ns, and the register setup time is 5 ns