Programmable Electronics Exercise Design Optimization and Performance Measures With a resource allocation constrained to one multiplier/divider, one subtractor, and one shift to perform the multiplication by 2, derive the Verilog design of the FDA that computes the equation: C = 2x/3-y/3x? Furthermore, perform the performance analysis if the equation is to be iterated for 50 times. Given the propagation delays for the components are multiplier/divider is 50 ns, subtractor is 10 ns, shifter is 5 ns, and the register setup time is 5 ns. Instructions: Your should contain: (1) The design of your FDA (DFG, schedule, resource allocation, RTL code, CS-Table, the functional block diagram of CU and DU), (2) Performance analysis (3) Verilog Program, the testbench program and the simulation waveform. (4) Discussion of your design and the results that you obtained. Programmable Electronics Exercise Design Optimization and Performance Measures With a resource allocation constrained to one multiplier/divider, one subtractor, and one shift to perform the multiplication by 2, derive the Verilog design of the FDA that computes the equation: C = 2x/3-y/3x? Furthermore, perform the performance analysis if the equation is to be iterated for 50 times. Given the propagation delays for the components are multiplier/divider is 50 ns, subtractor is 10 ns, shifter is 5 ns, and the register setup time is 5 ns. Instructions: Your should contain: (1) The design of your FDA (DFG, schedule, resource allocation, RTL code, CS-Table, the functional block diagram of CU and DU), (2) Performance analysis (3) Verilog Program, the testbench program and the simulation waveform. (4) Discussion of your design and the results that you obtained