Answer all parts please!

Problem $3$

A $2-$D rotation of the point $(x,y)$ by $$ radians is a very common operation in computer graphics and results in the point $(\stackrel{}{x}\frac{,}{b}ar(y)),$ where $\stackrel{}{x}=x*cos-y*sin$ and

$\frac{?}{\text{b}\text{a}\text{r}}(y)=x*sin+y*cos.$ Glossing over the exact number representation and bit manipulation, a circuit that computes this rotation can be represented as shown below.

Figure $3$: Circuit for Problem $3$ that computes a rotation of a $2-$D Cartesian coordinate.

For simplicity, assume that $t_{su}=t_h=t_{\text{w}\text{i}\text{r}\text{e}}=t_{clk}=0$ and that $t_{co}=10ns$ for all registers. The logic delays are as follows:

$-t_{cos}=100ns,t_{sin}=90ns$

$t_{\text{m}\text{u}\text{l}\text{t}}=60ns$

$t_{\text{a}\text{d}\text{d}}=25ns,t_{\text{s}\text{u}\text{b}}=30ns$

a$.$ Construct a Data Flow Graph $($DFG$)$ for the circuit. Label your three starting inputs $x,y,$ and $$ for each of the respective registers, and your outputs $\stackrel{}{x}$ and $\frac{?}{\text{b}\text{a}\text{r}}(y).$

b$.$ Draw two cut sets on your DFG$,$ one that makes a $2-$stage pipelined and one that makes a $3-$stage pipelined version of the circuit. Your pipelined circuits should

have the minimum possible clock periods. You should use two copies of your DFG or make sure that the different cut sets are clearly distinguishable on a single

DFG$.$

c$.$ Assuming we use the minimum clock periods, compute the latency for both your $2-$stage and $3-$stage pipelined versions of the circuit.