Answer all questions fully, making sure to show all work for full credit.

1.The ALU processor system developed in HW4 is going to be updated to include a memory element as shown in Figure 1. The memory system will contain a set of operation codes (opcodes) for the ALU to execute. The implementation of this memory system needs to be in the form of a register file that accepts a memory address and outputs the associated opcode stored at this address. Follow the steps below to update the ALU. The final design must be implemented using Verilog code within the Xilinx WebPack IDE.

a.A new module named memory must be developed for the processor system and connected to the ALU as shown in Figure 1. The input to the memory module is the address to an instruction desired to be executed and will be labeled PC (program counter). The output of the memory module is the instruction selected for execution. The register file in the memory module must be initialized using the mem.txt file from the course website. The mem.txt file includes instructions in the format shown in Figure 2. The modified ALU must be implemented using Verilog code within the Xilinx WebPack IDE for credit. (25 pts.)

1.The Digilent BASYS2 development board pin assignments for the complete system are listed in Table 1. Note that the operand values A and B and the output value Y are to be displayed on the 7-segment displays. Demonstrate the operation of your ALU on the BASYS 2 board to the instructor for credit. (15 pts.)

1.Develop a Verilog testbench to validate the memory module designed for the ALU system and implement it using Xilinx WebPack. Include the testbench code and associated results for full credit. (20 pts.)

LK operand A Operand B ALU Memory Code 7-Seg Display ANICA nf vf