Answer the following questions based on the following table. All different datapaths support the following four instruction types with listed delay of each component. Assume no hazard is detected in the pipelined datapath. Please explain your answer.

$\backslash$table$[[$Instruction class,$\backslash$table$[[$Instruction$],[$fotch$]],\backslash$table$[[$Register$],[$read$]],\backslash$table$[[$ALU$],[$operation$]],\backslash$table$[[$Data$],[$access$]],\backslash$table$[[$Register$],[$write$]],\backslash$table$[[$Total$],[$time$]]],[$Load word $($Iw$),200$ps$,100$ps$,200$ps$,200$ps$,100$ps$,800$ps$],[$Stcre word $($sw$),200$ps$,100$ps$,200$ps$,200$ps$,,700$ps$],[\backslash$table$[[$R$-$format $($add$,$ sub, and,$],[$or$,$ s $1$t$)]],200$ps$,100$ps$,200$ps$,,100$ps$,600$ps$],[$Branch $($beq$),200$ps$,100$ps$,200$ps$,,,500$ps$]]$

a$)$ What should clock cycle time be for the single$-$cycle and pipelined datapaths? Please explain your answer.

b$)$ What is the latency $($defined as the delay from when the instruction enters the datapath until it finishes$)$ of an $R-$format instruction in the single$-$cycle and pipelined datapaths?

c$)$ What is the latency $($defined as the delay from when the instruction enters the datapath until it finishes$)$ of load word $($lw$)$ instruction in the single$-$cycle and pipelined datapaths?

d$)$ What is the averaged throughput $($defined as the number of instructions executed in $1$ nanosecond in this case$)$ of the single$-$cycle and pipelined datapaths? Assume the frequency of four different instruction types are the same.