Answer the following questions based on the image shown below;

a) A 5-stage MIPS pipeline design is shown below. Highlight the EX and the MEM stages of the data path and control signals needed for executing beq instruction in this 5-stage MIPS pipeline. Note, you can circle the needed components and draw (bold) the line for the wires connecting these components.

b) In this design, how many stall cycles caused by beq without using any branch prediction mechanism (i.e. stalls are always inserted)?

c) You want to reduce one stall cycle without moving branch condition evaluation and target address calculation away from the EX stage. Describe qualitatively how you can accomplish this requirement

PCSr DNEX WB EX/MEM Control WB MEMWB EX WB FAD Add ShiftAdd Ad left 2 Branch PCAddress register 1 data 1 Read Zero ALU ALU register 2 Write Write Instruction Registers Read data 2 Address data MI Data Write 15-0 16 Sign-32 ALU ontrol 20-16 ALUOp (15-11 RegDst PCSr DNEX WB EX/MEM Control WB MEMWB EX WB FAD Add ShiftAdd Ad left 2 Branch PCAddress register 1 data 1 Read Zero ALU ALU register 2 Write Write Instruction Registers Read data 2 Address data MI Data Write 15-0 16 Sign-32 ALU ontrol 20-16 ALUOp (15-11 RegDst