Answer with good high level explanation please

A processor has a $4294967296-$byte data memory and a single data cache $($cache A$)$

containing $131072$ lines. Cache A is $1-$way set associative with a $256-$byte line size.

When the MIPS load byte instruction $lb$$$8,0($$$4)$ is executed, CPU register $$4$

contains the address of the final byte within memory block number $2928610.$

a$)$ Show the $8-$digit hex address contained in register $$4.$

b$)$ Suppose register $$6$ contains some unspecified memory address. Write down a

sequence of MIPS true$-$op instructions to compute the cache line number to which the

address in register $$6$ maps. The computed line number should be placed into register $$3.$

The instruction sequence should contain no more than two MIPS true$-$op instructions and

should work for any memory address contained in $$6$ without changing $$6.$

c$)$ Consider a different cache $($cache B$).$ Cache B contains $131072$ lines and is organized

as a $4-$way set associative cache. Each cache line is $256$ bytes in size. To what set within

this $4-$way set associative cache does the address $0$xC$306$DEFC map?

d$)$ Assume a reference to address $0xC306$DEFC causes a cache hit. Use hex to show the

tag for the cache line in which the hit occurs within Cache B$.$