ask to an expert the pdf $1.\backslash ((30\backslash )\text{'})$ Refreshing your knowledge learned from EE $210-$ Digital Design I or a similar course: Design a circuit $($see Figure $1)$ that has $4$ inputs, WXYZ$,$ and two outputs, f and g $,$ where W is the most significant bit $($MSB$)$ and Z is the least significant bit $($LSB$).$ The output f is asserted $(\backslash (\backslash$mathrm$\{$f$\}=\backslash )"1")$ whenever the two$-$bit number WX is greater than the two$-$bit number YZ $($i$.$e$.$ WX$>$YZ$).$ The output g is asserted $(\backslash (\backslash$mathrm$\{$g$\}=\backslash )"1")$ whenever the $4-$bit number represented by WXYZ$,$ is evenly divisible by $4.$

$1).$ List the truth table of the circuit based on its function description.

$2).$ Based on the truth table, draw the Karnaugh map of the circuit.

$3).$ Based on the Karnaugh map, determine SOP $($Sum$-$of$-$Product$)$ expression of the circuit. Based on the SOP realization, implement the circuit using $\backslash (\backslash$boldsymbol$\{$N A N D$\}\backslash )$ gates only. Sketch your gate level design.

$4).$ Now based on the Karnaugh map in $2),$ determine POS $($Product$-$of$-$Sum$)$ expression of the circuit. Based on the POS realization, implement the circuit using NOR gates only. Sketch your gate level design.

Hint: You should treat each outnut $($ f and $\backslash (\backslash$sigma $\backslash ))$ senarately and determine the truth tahle for each.

Figure $1.$ Design of a combinational logic circuit