Assignment $2$

Designing a Cache Simulato

You should get a confirmation email once it is uploaded successfully. You will develop your cache simulator to operate as with the cache memory we discussed in class and in your book. The cache will be configurable with following parameters:

Block size $($number of words. Note that we don't differentiate in this project for words and bytes. You can assume all addresses are referring to words, and no further byte$-$word conversion is needed$).$

You can assume all addresses are referring to word, needed$).$ Number of blocks in the cache. Associativity $(1$ for direct, $2$ for two$-$way set associative$)$ Hit time $($in ycles$)$

Your simulator should be able to handle direct mapped and $2-$way set$-$associative cache. You should use LRU $($least recently used$)$ replacement policy.

the testing guide$).$ Given this input and different configuration of your cache, compute the hit miss rate and the AMAT $($average memory access time$).$ You may hhoose reasonable values according to your need. Your program should also print out the final state of the cache using sett $($if applicable$),$ block#$,$ Valid bit and Tag.

Your cache only needs to support reads. You may choose C$/$C$++/$Python$/$Java$/$Matlab as your preferred language. The testing guideline is provided below:

Testing guide: The e esting procedure makes sure that your program is working correctly. In the grading process we will evaluate with the following two steps:

Step $1$: We are going to test with the following example $(\text{'}$Test$1.$txt$\text{'})$ to verify that your code is working. Your solution should give the same result as below:

Suppose that there are a series of address references given as word addresses: $0,3,11,16,21,11,16,48,16.$ Show a$)$ Show

a$)$ Show the hits and miss a total size of $16$ words.

b$)$ Show the hits and misses and final cache contents for a two$-$way set$-$associative cache and a total size of $16$ words. sssume LRU replacement. $($Hint: there is a total of eight sets in this case$)$ Solution:

$16$ words. A Solution:

a$)$ Here is the hit and miss history for the memory accesses: $($Summary: the second $11$ and the second $16$ are hits, all others are misses$)0($miss$),($miss$),11($miss$),16($miss$),2($miss$),11($hit$),16($hit$))48($miss$),16($miss$)$ Contents in the cache at the end, in the format of $($address: content$)$:

$0$:$16,3$:$3,5$:$21,11$:$11$ The output of your program should be:

b$)$ The second $11,$ the second and the third $16$ are hits, all others are misses. $0($miss$),3($miss$),11($miss$),16($miss$),21($miss$),11($hit$),16($hit$),48($miss$),16($hit$)$

HTT $=61$ MISS $=9939$ HIT RATE $0\mathrm{.}0061$ MISS RATE $=0\mathrm{.}9939$

On the other hand, if we increase the block size to $256$ words, with a total of $256$ blocks, the result becomes:

HIT $=978$ MISS $=9022$ HIT RATE $=0\mathrm{.}0978$ MISS RATE $=0\mathrm{.}9022$

Your program should also print out the using sett, block"t$,$ Valid bit and Tag.

Your program should also print out using sett, blockt, valid bit and Tas

Extra Extra Credit $(25$ points$)$

Designg a text file containing a sequence of read addresses $(25-35$ addresses$)$ that clearly shows the difference between direct mapped and $2-$way set associtive cache. Demonostrate the difference with output