Deadline: $22$ December $2024,23$:$59$ PM

$1.$ Introduction

In this lab, you will build a $2-$way set associative cache memory for MIPS $32-$bit processor as shown in Figure $1$ using SystemVerilog. Before starting this lab, you should be very familiar with the $\backslash ($ N $\backslash )-$way set associative cache with least recently used $($LRU$)$ replacement described in Section $8\mathrm{.}3$ of your textbook.

Set $3(11)$ Set $2(10)$ Set $1(01)$ Set $0(00)$

Figure $1$: $2-$way set associative cache for MIPS $32-$bit processor

$2.$ Designing the cache memory

As shown in Figure $1,$ the $2-$way set associative cache memory will have the capacity of eight words. Initializing all fields of the cache with $0\text{'}$s when the system starts. It will receive a $32-$bit address $($addr$),$ a clock $($clk$)$ signal and a reset $($rst$)$ signal as input. In case of a low reset signal, initializing all fields of the cache with $0\text{'}$s$.$ The cache should be accessed and updated at each of the negative edge of the clk$.$ Then it will return $1-$bit hit signal and the $32-$bit data. In case of hit, the data from the right block of a set should be returned with the value of hit $\backslash (=1\backslash ).$ Otherwise, the data should be uploaded to the cache from the main memory, LRU block should be replaced in case of the set is full, and the replaced data should be retuned with hit $\backslash (=0\backslash ).$ Assume that the data of a particular address of the main memory is: addr$/4.$ The SystemVerilog module definition with a possible outline for the cache memory for the $32-$bit MIPS processor is as follows: $```$

module cache $($input logic $[31$:$0]$ addr, input logic clk$,$ rst$,$ output logic $[31$:$0]$ out, output logic hit $)$;

$//$ Define necessary logics here

$//$ Initializing all fields of the cache with $0\text{'}$s when the system starts

initial

begin

$//$ write your code here

end

$//$ Initializing all fields of the cache with $0\text{'}$s in case of a low reset signal

always @$(*)$

begin

if $($rst $==1\text{'}$b$0)$

begin

$//$ write your code here

end

end

$//$ The cache should be accessed and updated at each of the negative edge of the clk

always @$($negedge clk$)$

begin

if$($rst $==1\text{'}$b$1)$

begin

$//$ write your code here

end

end

endmodule

$```$

$3.$ Testing the cache memory

Simulate your cache with EDA Playground. Be sure to add all of the $.$sv files. Now run the test bench as given below $($also uploaded on LMS as testBench$3$p$3\_$Student.sv$)$:

$```$

$//$ Testbench for $2-$Way set Associate cache for MIPS processor

$//$ saiful.islam@tedu.edu.tr$,12$ Dec $2024$

$//-----------------------------------------------$

$//\text{'}$timescale $1$ns$/1$ps

module tb;

logic clk$,$ rst;

logic$[31$:$0]$ addr;

logic$[31$:$0]$ out;

logic hit;

$``````$

int tests $=0,$ errors $=0$;

cache dut$(.$addr$($addr$),$

$.$clk$($clk$),$

$.$rst$($rst$),$

$.$out$($out$),$

$.$hit$($hit$)$

$)$;

always #$5$ clk $=$ ~clk;

initial

begin

clk $=1\text{'}$b$0$;

rst $=1\text{'}$b$1$;

addr $=32\text{'}$h$0$; #$5$

tests $=$ tests$+1$;

$strobe$("$Result: hit $=\%1$b$,$ data $=0$x$\%$x$",$ hit, out$)$;

if $($ hit $===0$ & out $===0)$

$strobe$("[$Test Successfull...$]")$;

else

begin

$strobe$("[$Test failed: Expected hit $=\%1$b$,$ data $=0$x$\%$x$]",0,0)$;

errors $=$ errors$+1$;

end #$5$

addr $=32\text{'}$h$4$; #$5$

tests $=$ tests$+1$;

$strobe$("$Result: hit $=\%1$b$,$ data $=0$x$\%$x$",$ hit, out$)$;

if $($ hit $===0$ & out $===1)$

$strobe$("[$Test Successfull...$]")$;

else

begin

$strobe$("[$Test failed: Expected hit $=\%1$b$,$ data $=0$x$\%$x$]",0,1)$;

errors $=$ errors$+1$;

end #$5$

addr $=32\text{'}$h$0$; #$5$

tests $=$ tests$+1$;

$strobe$("$Result: hit $=\%1$b$,$ data $=0$x$\%$x$",$ hit, out$)$;

if $($ hit $===1$ & out $===0)$

$strobe$("[$Test Successfull... $]")$;

else

begin

$strobe$("[$Test failed: Expected hit $=\%1$b$,$ data $=0$x$\%$x$]",1,0)$;

errors $=$ errors$+1$;

end #$5$

addr $=32\text{'}$h$40$; #$5$

tests $=$ tests$+1$;

$strobe$("$Result: hit $=\%1$b$,$ data $=0$x$\%$x$",$ hit, out$)$;

if $($ hit $===0$ & out $===32\text{'}$h$10)$

$``````$

$strobe$("[$Test Successfull... $]")$;

else

begin

$strobe$("[$Test failed: Expected hit $=\%1$b$,$ data $=0$x$\%$x$]",0,32\text{'}$h$10)$;

errors $=$ errors$+1$;

end #$5$

$//$Reset the cache

rst $=1\text{'}$b$0$;

#$10$

rst $=1\text{'}$b$1$;

addr $=32\text{'}$h$4$; #$5$

tests $=$ tests$+1$;

$strobe$("$Result: hit $=\%1$b$,$ data $=0$x$\%$x$",$ hit, out$)$;

if $($ hit $===0$ & out $===1)$

$strobe$("[$Test Successfull...$]")$;

else

begin

$strobe$("[$Test failed: Expected hit $=\%1$b$,$ data $=0$x$\%$x$]",0,1)$;

errors $=$ errors$+1$;

end #$5$

$```$

$```$

$display$("\backslash$t Total tests: $\%$d

$",$ tests$)$;

$display$("\backslash$t Total errors: $\%$d

$",$ errors$)$;

$display$("======================================================================")$;

$finish;

end

endmodule

$```$