ASSIGNMENT 3 Q1: In the MIPS/ARM processor architecture, that discussed during the course lectures: Write all the steps to execute the Store Word (SW) instruction. Your answer should show the execution step-by-step as following: 1-set the PC value of SW 2-Access instruction memory3-Provide SW instruction to Control Unit and Register File (RF) access continues until the instruction execution completed. 02: Repeat Q1 for Branch Equal instruction. the executionstep Control Unitand Register File(RFfSW2-Access instruction m Q3: Write the control signals that has to be generated by the control for the following instructions a) b) Store Half World (SHW): This instruction store 16 bits in data memory Branch Not Equal (BNQ): Branch to the target address if two sources registers are not equal instruction RegWrite RegDest Alusrc Memwrite MemtoReg ASSIGNMENT 3 Q1: In the MIPS/ARM processor architecture, that discussed during the course lectures: Write all the steps to execute the Store Word (SW) instruction. Your answer should show the execution step-by-step as following: 1-set the PC value of SW 2-Access instruction memory3-Provide SW instruction to Control Unit and Register File (RF) access continues until the instruction execution completed. 02: Repeat Q1 for Branch Equal instruction. the executionstep Control Unitand Register File(RFfSW2-Access instruction m Q3: Write the control signals that has to be generated by the control for the following instructions a) b) Store Half World (SHW): This instruction store 16 bits in data memory Branch Not Equal (BNQ): Branch to the target address if two sources registers are not equal instruction RegWrite RegDest Alusrc Memwrite MemtoReg