Assume a hypothetical system with eight $32-$bit words cache and small

Main memory of $3$ bits to address cache words and $8$ bitste. if you

know that we words. If the system uses Fully Associative address

Min memory we content by the following picture: Complepping

given the cacle by typing Hit or Miss for each request madele the

following tabic by made by the

CPU b$.$ If the system uses Fully Associative mapping given the cache content by the following

picture:

Main Memory