Question: Assume that the system uses a 3 2 - bit address. ( RISC - V architecture ) a . Consider a cache with 3 2

Assume that the system uses a 32-bit address. (RISC-V architecture)
a. Consider a cache with 32MB of data,4-way set associativity, and 128-byte line (block)
size. What is the size of each line's tag in bits?
b. Consider a cache with 512 sets, 4-way set associativity, and 9-bit tags. How many bytes
can the cache store? (What is the data capacity not including overhead of storing tags,
valid bits, etc.?)
Assume that the system uses a 3 2 - bit address.

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