Consider the following RISC V Code $($use this data for both $($a$)$ and $($b$)$ subparts:

addi s$0,$ zero, $2$

L$1$:

lw t$1,0($s$1)$

beq t$1,$ s$2,$ FD

addi s$1,$ s$1,4$

addi s$0,$ s$0,-1$

bne s$0,$ zero, L$1$

jal zero, NFD

FD: addi s$0,$ zero, $1$

NFD: sw s$0,0($s$3)$

$[$Assume that s$1$ contains $0$x$10010000,$ which is starting

address of an array which consists of words which are

powers of $2$ till $16.$

e$.$g$.$

$0$x$00000001,0$x$00000002,0$x$00000004,...$

$0$x$00000010.$

Assume s$2$ contains $0$x$00000002]$

$($a$)$ Assume that normal $5-$stage pipelined processor $($discussed in class$),$ which supports EX$-$to$-$EX and

MEM$-$to$-$EX forwarding and Hazard detection, is used to execute the above program. Assume the

processor uses predict not$-$taken static branch predictor. For each instruction, determine the clock cycle

$($numbers$)$ in which it enters IF$,$ ID$,$ EX$,$ Mem and WB stage. If any instruction does not enter a particular

pipeline stage, then you can mark NA or $$ in the corresponding column. If any instruction is executed

more than once, all the clock cycle numbers in which the instruction enters the pipeline stage should be

mentioned separated by a semicolon. $[$For example, if lw t$1,0($s$1)$ instruction enters instruction fetch twice

$($because of looping$)$ once in $2$nd clock cycle and second time in $11$th clock cycle then in the column

corresponding to IF you have to write $2$; $11]$