Assume that the write$-$back invalidating snooping protocol is adopted to a multi$-$core computer architecture. In this architecture, a processor can address $64$KB main memory and have a $4-$way set$-$associative write$-$back cache with $64$ sets and $16$ bytes per line. The settings for this architecture is listed as follows: $(7)$ A LRU replacement policy is implemented on the cache. $6)$ Two caches for two processors are empty at the beginning, and the memory is accessed by the following sequence. Please show the information of the tag, set, line number, directory$-$based state, data for non$-$empty cache lines, and the contents of memory by using Tables $1$ and $2$ format after each step of data accesses. $(32$ pts$,4$ pts for each step$)[1].$ Processor $0$ reads from location $0$ D $3$ C $[2].$ Processor $1$ writes $0110$ to location OD$34[3].$ Processor $0$ reads from location OD$38[4].$ Processor $1$ writes $1111$ to location $1$D$34[5].$ Processor $0$ writes $0001$ to location $1$D$3$C $[6].$ Processor $0$ reads from location $0$ D $3$ C $[7].$ Processor $1$ writes $1110$ to location $2$D$30[8].$ Processor $0$ reads from location $2$ D $3$ C Table $1.$ The information in caches Table $2.$ Initial state of memory