"Assume the code sequence give below:

add t$6,$ s$6,$ s$1$

slt t$9,$ t$1,$ s$4$

sub t$3,$ t$0,$ t$5$

sub s$7,$ t$7,$ t$8$

nor s XR$020,$ s$7,$ s$5$

lw s$3,61($t$3)$

beq t$6,$ s$2,$ FOR

FOR:

And assume the $5-$stage pipeline discussed in the learning objective:

Instruction Fetch $($IF$)$

Register Read $($RR$)$ aka Instruction Decode $($ID$)$

ALU Operation $($ALU$)$ aka Execution $($EX$)$

Data Memory $($DM$)$

Register Write $($RW$)$ or Write Back $($WB$)$

Practice $1$:

Find RAW Data Hazard in the sequence and enter on the designated cell of the sheet:

Register

Producer Instruction

Consumer Instruction

RAW Dependency $1$

RAW Dependency $2$

RAW Dependency $3$

Practice $3$:

Considering the data hazard you have found in Practice $1$ and the control hazard, show pipeline execution of the sequence when:

There is no Forwarding capability available in the hardware

Prediction as a solution for control hazard and predictor is correct

Show the pipeline execution by completing the table below:

$1$

$2$

$3$

$4$

$5$

$6$

$7$

$8$

$9$

$10$

$11$

$12$

$13$

$14$

$15$

$16$

$17$

$18$

$19$

$20$

$21$

$22$

add t$6,$ s$6,$ s$1$

IF

RR

EX

DM

RW

slt t$9,$ t$1,$ s$4$

sub t$3,$ t$0,$ t$5$

sub s$7,$ t$7,$ t$8$

nor s$0,$ s$7,$ s$5$

lw s$3,61($t$3)$

beq t$6,$ s$2,$ FOR"