Assume the following instruction is to be executed using the 5-cycle LEGv8 pipeline architecture explained in class:

LDUR X1, [X2, #500]

Assume Reg[X1] = 16, Reg[X2] = 10, and Mem[510] = 15. Fill out the following table, showing the micro-instructions executed and the values of the registers at the end of each pipeline cycle. Use \?" for registers whose values are not known in a cycle. Assume this is the only instruction entering into the pipeline, so no other instructions can a ect the outcomes of the registers. Note: You need to show the micro-instructions executed in each stage and Not the name of the stage.

Note that each entry of the table carries some points. Points will be deducted for leaving an entry blank. Stage Micro. Insts. A B Imm ALUOUT2LMD X1 X2 2 3 4 5 Note that each entry of the table carries some points. Points will be deducted for leaving an entry blank. Stage Micro. Insts. A B Imm ALUOUT2LMD X1 X2 2 3 4 5