Assume the following instruction is to be executed using the 5-cycle pipeline architecture explained in class:

LW R1, 500(R2)

Assume Reg[R1] = 16, Reg[R2] = 10, and Mem[510] = 15. Fill out the following table, showing the microinstructions executed and the values of the registers at the end of each pipeline cycle. Use "?" for registers whose values are not known in a cycle. Assume this is the only instruction entering into the pipeline, so no other instructions can affect the outcomes of the registers.

Stage	Micro. Insts.	A	B	Imm	ALU OUTPUT	LMD	R1	R2
1
2
3
4
5