Assume the following non-optimized code runs on an older single-issue architecture with a processor that has perfect branch prediction, and has hazard detection and forwarding that includes forwarding to the ID stage (for branch resolution). sd x25, 120 (23) sub x29, x25, x24 add x4, x8, x9 ld x10, 100 (16) id x26, 60 (x29) srli x28, x31, 10 sd x28, 120 (23) addi x30, 31, 1 A compiler rearranges this code to run on a static dual-issue pipeline. Compiler makes sure that memory-access instructions are paired with arithmetic or logic instructions. It further ensures that two instructions in which one depends on the other do not issue together (not fetched at same cc). Paired instructions are stalled together. a) Rearrange the code to run on the modern dual issue pipeline; b) Draw the graphical pipeline representation of the single-issue architecture executing the initial code. Assume CC1 is when sd is fetched; c) Draw the graphical pipeline representation of the dual-issue architecture executing the rearranged code; d) What is the performance improvement of the dual-issue architecture executing the rearranged code versus the pre-arranged code executing on a single-issue architecture? Assume clock cycle duration is same for both architectures. Explain. Assume the following non-optimized code runs on an older single-issue architecture with a processor that has perfect branch prediction, and has hazard detection and forwarding that includes forwarding to the ID stage (for branch resolution). sd x25, 120 (23) sub x29, x25, x24 add x4, x8, x9 ld x10, 100 (16) id x26, 60 (x29) srli x28, x31, 10 sd x28, 120 (23) addi x30, 31, 1 A compiler rearranges this code to run on a static dual-issue pipeline. Compiler makes sure that memory-access instructions are paired with arithmetic or logic instructions. It further ensures that two instructions in which one depends on the other do not issue together (not fetched at same cc). Paired instructions are stalled together. a) Rearrange the code to run on the modern dual issue pipeline; b) Draw the graphical pipeline representation of the single-issue architecture executing the initial code. Assume CC1 is when sd is fetched; c) Draw the graphical pipeline representation of the dual-issue architecture executing the rearranged code; d) What is the performance improvement of the dual-issue architecture executing the rearranged code versus the pre-arranged code executing on a single-issue architecture? Assume clock cycle duration is same for both architectures. Explain