Question: Assume the reference inverter with equal rise and fall delay has a PFET with 1 fin and an NFET with 1 fin. Size the gates

Assume the reference inverter with equal rise and fall delay has a PFET with 1 fin and an NFET with 1 fin. Size the gates in the 3 chains below for minimum delay and equal rise and fall times at each stage. Assume the first stage in this chain is a reference inverter (a total load of 2 fins) and the last stage drives CL - a total load of 1000 fins

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