We want to generate the function r. (y+z)+y.z in a single stage of a CMOS static...

Transcribed Image Text:

We want to generate the function r. (y+z)+y.z in a single stage of a CMOS static style logic gate by scaling transistor geometries from a reference inverter, using series parallel rules. Width of the n channel transistor in the reference inverter is taken as the unit of width. Width of the p channel transistor is y times this unit to compensate for the mobility difference between electrons and holes. Wiring and self capacitance delays are to be ignored. The delay of a reference inverter driving another is T. a) Draw a transistor level schematic for this gate, specifying the width of each tran- sistor such that the output drive of the gate is the same as that for the reference inverter (for the worst case input logic value) and the capacitive loading on the inputs is minimized. Verify this using a simple equivalent resistor analogy. b) While x.y + y.z+z.x is symmetric in x, y and z, our implementation of this func- tion as x. (y + 2) + y.z is not symmetric. If one of the inputs of this implementation is to be placed in the critical path of a design, which input will you choose? Justify your choice. If this critical path input is coming from an identical stage before it, compute the delay of the previous stage when loaded with your choice of input (x, y or z), in units of T. We want to generate the function r. (y+z)+y.z in a single stage of a CMOS static style logic gate by scaling transistor geometries from a reference inverter, using series parallel rules. Width of the n channel transistor in the reference inverter is taken as the unit of width. Width of the p channel transistor is y times this unit to compensate for the mobility difference between electrons and holes. Wiring and self capacitance delays are to be ignored. The delay of a reference inverter driving another is T. a) Draw a transistor level schematic for this gate, specifying the width of each tran- sistor such that the output drive of the gate is the same as that for the reference inverter (for the worst case input logic value) and the capacitive loading on the inputs is minimized. Verify this using a simple equivalent resistor analogy. b) While x.y + y.z+z.x is symmetric in x, y and z, our implementation of this func- tion as x. (y + 2) + y.z is not symmetric. If one of the inputs of this implementation is to be placed in the critical path of a design, which input will you choose? Justify your choice. If this critical path input is coming from an identical stage before it, compute the delay of the previous stage when loaded with your choice of input (x, y or z), in units of T.

Answer rating: 100% (QA)

The detailed ... View the full answer