Assume we have a fully-associative LRU cache. The LRU caching scheme is to remove the least recently used item when the cache is full. The cache block size is 2 values, and the overall cache size is 4 blocks. Simulate the cache behavior by hand when reading the following sequence of memory addresses, starting with an empty cache. To simplify this problem, we will ignore the word size. Thus, each non-negative integer is taken to be a memory address of a distinct word. In other words, we can read or write a value to each non-negative integer address. After these reads, which memory addresses are replicated in the cache? \begin{tabular}{l} 6,7,8,910,11,12,13 \\ 6,7,10,11,12,13,98,99 \\ 6,11,12,99 \\ \hline 4,5,6,7,8,9,10,11,12,13,98,99 \\ \hline 8,9,10,11,12,13,14,15 \\ \hline 6,7,8,9,10,11,98,99 \end{tabular}