Assume you have a computer with L1 data cache and a main memory. (Focus only on data access and don't worry about memory access). Latencies of different kinds of accesses are as follows: Cache hit Cache miss 1 Cycle 110 cycles Main memory access with cache disabled 105 cycles A) What will be the Average memory access time when you run the program with an overall miss rate of 3% ? B) What will be the Average memory access time when you run the program with an hit rate of 108 cycles.