Assume you want to create a 9-input NOR function by having 3 3-input NORs each driving one input of a 3-input NAND, whose output drives an inverter, and whose output of that invertor driving 10 unit inverters.

a. What size transistors might you use in the NORs, NAND, and inveter for minimum delay/

What is that delay?

b. What would have been the delay if you had built one giant 9-input NOR gate using your

computations from problem 2?