Assuming a large $10ns$ PLD was used to generate each product component bit and implement each full adder cell, the worst case propagation delay of a $44$ unsigned binary multiplier array would be ns$.$

$($A$)60$

$($B$)70$

$($C$)80$

$($D$)90$

Assuming the CF condition code bit is initially cleared, a sequence of arithmetic operations to verify that CF was properly set and subsequently cleared is $($A$)1111-1110$ followed by $1111+1110$

$($B$)0010-0011$ followed by $0010+0011$

$($D$)0001-1110$ followed by $0001+1110$