Assuming a non$-$pipelined processor described by the logic diagram given above as well as the times

listed in the table. You may assume the register setup time $($RSET$)$ is negligible for all registers including

PC$.$ Please answer the following questions:

a$)$ If we only wanted to support branch instructions $($e$.$g$.$ BEQ$),$ what would be the cycle time for

this Datapath $($be sure to show the critical path and your calculations$)?$

b$)$ If we only wanted to support ALU I$-$type instructions $($ADDI$,$ ORI, etc.$),$ what would be the cycle

me for this Datapath $($be sure to show the critical path and your calculations$)?$

c$)$ What would be the best frequency that could support this path?