Assuming that each SRAM listed in the table below has $8$ output lines:

a$)$ If it is arranged optimally, how many rows and columns are in the organization?

b$)$ What is the size of the column multiplexer?

c$)$ Draw the logic gate$-$level schematic for an $8-$bit active$-$low binary decoder that takes inputs

$S_2{S}_1{S}_0$ and produces outputs $d_0$:$d_7,$ where $d_0$ is selected when $S_2{S}_1{S}_0=000.$