b$)$ Consider the following program to be executed on a processor with two fetch units, two decode units, two write units.

and four ALUs $($Add$,$ Mul, Load, Logic$).$ The processor issues two$-$instructions per cycle.

$I_1$ : Load $R_2,B$

$I_2$ : Sub $R_2,R_3$

$I_3$ : $M$ ul $R_2,R_4$

I. : Comp Rs

Is: Mul R$6,$ R$5$

Show the pipeline activity for this program using in$-$order issue with out$-$of$-$order execution