Q$1$ Consider the $8-$stage pipelined processor with two execution units and pipelined caches, as shown below. Instruction fetch is a two$-$stage process followed by decode where registers are also read in the second half of the cycle. Additionally, the pipeline consists of a separate exccution unit for floating point $($FP$)$ operations. First unit is for all Integer Arithmetic$/$Branch operations $($excluding multiply$),$ consisting of one stage. Second unit is for floating point $($FP$)$ Add$/$Sub and Multiply $($both integer and FP$)$ operations, comprising four stages. The data cache is pipelined and takes three stages for read$/$write opcrations $($including integer and IP loads and stores$).$ The final stage performs registers writes in the first half of the cycle, if any. $[$CI$.$O$-1,$ C$-30$ Integer Add$/$Sub$)$ Data Memory Ld$/$St & Branch Instruction Fetch Decode M$1$ H M$2$ M$3$ RW EX$-1$ EX$-2$ EX$-3$ EX$-4[1][1]$ Consider the clock cycle time for the above pipeline to be $250$ ps and assumc cach stage takes equal time. a$)$ Compute the latency of $"$LD$"$ Instruction to load Double Precision Floating Point number. b$)$ Calculate the latency of "MUL.F$",$ FP multiply instruction. c$)$ Assuming there are no FP and multiply instructions in a program, comparing with a five$-$ stage MIPS pipeline compute how fast can the program run on this processor. Assume the cycle time for MIPS to be $400$ ps$,$ and no extra stall cycles due to hazards. d$)$ Determine what happens if register reads are performed in the first half of the cycle. e$)$ Create a sequence consisting of FP and Integer instructions and show through pipeline diagram that no structural hazards exist in this design. $1)$ Determine how many stall cycles should be inserted between a load instruction and the different classes of instructions that use the load's result during the execution stage. g$)$ Considering that branch target address is calculated in ID stage and condition evaluated in EX$,$ determine how many stall cycles should be inserted between the following instructions considering no forwarding unit is available. $1.$ ADD R$1,$ R$2,$ R$32.$ BNE R$3,$ R$2,$ addr! $[2][2][3][1]$