b) Given a machine with a 6-stage pipeline (Fetch, Decode, Execute, Memory Access First, Memory-Access Second, Write-Back), assuming that 3 instructions independent of each other need to be executed, fill the table with the detailed stages that will occur in each clock cycle and write down how many clock cycles needed to finish the whole execution of the 4 instructions, you could draw the table in your answer sheet and add rows as many as you need. [6 marks] Time Details 1 2 3