(b) In a 5-stage DLX pipeline, state all operational events for a branch instruction at each...

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(b) In a 5-stage DLX pipeline, state all operational events for a branch instruction at each stage during its execution. (6 marks) (c) A single processor is modified with the typical 5-stage instruction pipeline implemented. A benchmark program is tested in the 5- stage pipelined machine. It is recorded that the pipeline stall cycles per instruction are 0.45. When the forwarding technique is enabled, this value is reduced to 0.11. ● Calculate how much performance gain is due to the forwarding technique. Calculate the overall speedup gained from pipelining. State assumptions you make in the calculate and keep your result to 2 decimal digits. (8 marks) (b) In a 5-stage DLX pipeline, state all operational events for a branch instruction at each stage during its execution. (6 marks) (c) A single processor is modified with the typical 5-stage instruction pipeline implemented. A benchmark program is tested in the 5- stage pipelined machine. It is recorded that the pipeline stall cycles per instruction are 0.45. When the forwarding technique is enabled, this value is reduced to 0.11. ● Calculate how much performance gain is due to the forwarding technique. Calculate the overall speedup gained from pipelining. State assumptions you make in the calculate and keep your result to 2 decimal digits. (8 marks)