This exercise is intended to help you understand the cost/complexity/ performance trade-off s of forwarding in a
Question:
Figure 4.45
1. If we use no forwarding, what fraction of cycles are we stalling due to data hazards?
2. If we use full forwarding (forward all results that can be forwarded), what fraction of cycles are we staling due to data hazards?
3. Let us assume that we cannot afford to have three input Muxes that are needed for full forwarding. We have to decide if it is better to forward only from the EX/MEM pipeline register (next-cycle forwarding) or only from the MEM/WB pipeline register (two-cycle forwarding). Which of the two options results in fewer data stall cycles?
4. For the given hazard probabilities and pipeline stage latencies, what is the speedup achieved by adding full forwarding to a pipeline that had no forwarding?
5. What would be the additional speedup (relative to a processor with forwarding) if we added time-travel forwarding that eliminates all data hazards? Assume that the yet-to-be-invented time-travel circuitry adds 100 ps to the latency of the full-forwarding EX stage.
6. Repeat 4.12.3 but this time determine which of the two options results in shorter time per instruction.
Step by Step Answer:
Computer Organization and Design The Hardware Software Interface
ISBN: 978-0124077263
5th edition
Authors: David A. Patterson, John L. Hennessy