This exercise is intended to help you understand the cost/complexity/ performance trade-off s of forwarding in a pipelined processor. Problems in this exercise refer to pipelined datapaths from Figure 4.45. These problems assume that, of all the instructions executed in a processor, the following fraction of these instructions have a particular type of RAW data dependence. The type of RAW data dependence is identified by the stage that produces the result (EX or MEM) and the instruction that consumes the result (1st instruction that follows the one that produces the result, 2nd instruction that follows, or both). We assume that the register write is done in the first half of the clock cycle and that register reads are done in the second half of the cycle, so €œEX to 3rd€ and €œMEM to 3rd€ dependences are not counted because they cannot result in data hazards. Also, assume that the CPI of the processor is 1 if there are no data hazards.

Figure 4.45

1. If we use no forwarding, what fraction of cycles are we stalling due to data hazards?

2. If we use full forwarding (forward all results that can be forwarded), what fraction of cycles are we staling due to data hazards?

3. Let us assume that we cannot afford to have three input Muxes that are needed for full forwarding. We have to decide if it is better to forward only from the EX/MEM pipeline register (next-cycle forwarding) or only from the MEM/WB pipeline register (two-cycle forwarding). Which of the two options results in fewer data stall cycles?

4. For the given hazard probabilities and pipeline stage latencies, what is the speedup achieved by adding full forwarding to a pipeline that had no forwarding?

5. What would be the additional speedup (relative to a processor with forwarding) if we added time-travel forwarding that eliminates all data hazards? Assume that the yet-to-be-invented time-travel circuitry adds 100 ps to the latency of the full-forwarding EX stage.

6. Repeat 4.12.3 but this time determine which of the two options results in shorter time per instruction.

sub $11, $2, $3 Iw $13, 24 ($1) Iw $10, 20(S1) add $14, $5, $6 add $12, $3, $4 Instruction fetch Instruction decode Execution Memory Write-back MEMWB IFAD IDVEX EXMEM Add Ags A Trosuth Shift let 2 Addrass Read Taghlar Read data Read Zero ALU ALU ragistar 2 Registors Ruad Write agistar Instruction Read Addross momory resut data data 2 Data Write data memory Write data 16 Sign- axtand EX (FW from MEM/ WB only) EX EX EX (FW from (no FW) (full FW) EX/MEM only) MEM WB IF ID 150 ps 130 ps 120 ps 100 ps 100 ps 120 ps 150 ps 140 ps